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課程名稱	積體電路測試 VLSI TESTING
開課學期	99-1
授課對象	電機資訊學院電子工程學研究所
授課教師	李建模
課號	EEE5001
課程識別碼	943EU0010
班次
學分	3
全/半年	半年
必/選修	選修
上課時間	星期三2,3,4(9:10~12:10)
上課地點	電二225
備註	本課程以英語授課。本課程以英語授課。總人數上限：80人
Ceiba 課程網頁	http://ceiba.ntu.edu.tw/991_vlsitesting
課程簡介影片
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課程概述	This course introduces test techniques for VLSI circuits. Important issues and their solutions will be covered. Homework includes hand written and computer assignments (in C or C++). A final team project is also required. outline INTRODUCTION LOGIC SIMULATION FAULT MODELING FAULT SIMULATION TESTABILITY ANALYSIS COMBINATIONAL ATPG SEQUENTIAL ATPG DELAY TESTS FUNCTIIONAL TESTS DIAGNOSIS DESIGN FOR TESTABILITY BUILT-IN SELF TEST MEMORY TESTING SOC TESTING
課程目標	Learn the important VLSI testing techniques. Be able to implement test-related algorithms in computer programs. Team work with other students to solve specific problem in testing.
課程要求	GRADING HOMEWORK: 40% EXAM: 30% TERM PROJECT: 30% PARTICIPATION 2% PREREQUISITES LOGIC DESIGN COMPUTER PROGRAMMING
預期每週課後學習時數
Office Hours	另約時間
指定閱讀	NONE
參考書目	WANG, WU, WEN, "VLSI TEST PRINCIPLES AND ARCHITECTURES, MORGAN KUFFMAN, 2006. M.L. BUSHNELL, V.D. AGRAWAL, “ESSENTIALS OF ELECTRONIC TESTING,” KLUWER ACADEMIC PUBLISHERS, 2000. M. ABRAMOVICI, M.A. BREUER, AND A.D. FRIDEMAN, “DIGITAL SYSTEMS TESTING AND TESTABLE DESIGN,” IEEE PRESS 1995.
評量方式 (僅供參考)

課程進度

週次	日期	單元主題
Week 1		Introduction
Week 2		Fault Modeling Fault Collapsing
Week 3		Logic Simulation, fault sim
Week 4		Testability Measure Comb. ATPG
Week 5		Comb. ATPG
Week 6		Sequential ATPG
Week 7		Delay Tests
Week 8		Int'l test conf. no class
Week 9		Diagnosis
Week 10		BIST (1)
Week 11		BIST (2)
Week 12		Memory Testing (slides revised 11/30)
Week 13		Design for Testability (1) + project presentation
Week 14		Design for Testability (2)
Week 15		Test Compression/SOC test
Week 16		functional testing or other topics
Week 17		Final Exam
Week 18		Project Presentation